package group
import chisel3._
import chisel3.util.RegEnable

trait chip_config{
  val DATA_BW   = 2
  val RESULT_BW = 8
  val Daisy_BW  = 4
  val CHIP_NUM  = 16
}

class chip_IO extends Bundle with chip_config {
  val fpga_cim_data = Input(UInt(DATA_BW.W))
  val fpga_cim_cmd  = Input(Bool())
  val cim_fpga_state= Output(Bool())
  val cim_fpga_clk  = Output(Clock())
  val cim_fpga_result = Output(UInt(RESULT_BW.W))
}

class emitter_IO extends Bundle with chip_config {
  val fpga_cim_data = Input(UInt(DATA_BW.W))
  val fpga_cim_cmd  = Input(Bool())
  val cim_fpga_state= Output(Bool())
  val cim_fpga_result = Output(UInt(RESULT_BW.W))
}
class emitter extends RawModule with chip_config {
  val io = IO(new Bundle{
    val systemclk = Input(Clock())
    val systemRstn = Input(Bool())
    val enable    = Input(Bool())
    val emitterio = new emitter_IO
    val chipio    = Flipped(new chip_IO)
  })
  val systemRst = !io.systemRstn
  withClockAndReset(io.systemclk,systemRst){
    val data = RegEnable(io.emitterio.fpga_cim_data,0.U,io.enable)
    val cmd  = RegEnable(io.emitterio.fpga_cim_cmd,false.B,io.enable)
    io.chipio.fpga_cim_data     := data
    io.chipio.fpga_cim_cmd      := cmd
  }
  val u_BUFG = Module(new BUFG).io
  u_BUFG.I := io.chipio.cim_fpga_clk
  withClockAndReset(u_BUFG.O,systemRst){
    val state = RegEnable(io.chipio.cim_fpga_state,false.B,io.enable)
    val result= RegEnable(io.chipio.cim_fpga_result,0.U,io.enable)
    io.emitterio.cim_fpga_state   := state
    io.emitterio.cim_fpga_result  := result
  }
}




